https://doi.org/10.1140/epjqt/s40507-023-00201-1
Research
Soft syndrome iterative decoding of quantum LDPC codes and hardware architectures
1
Department of Electrical and Computer Engineering, The University of Arizona, Tucson, USA
2
Instituto de Telecomunicaciones y Aplicaciones Multimedia, Universitat Politecnica de Valencia, Valencia, Spain
3
Department of Computer Architecture and Automatics (DACYA), Complutense University of Madrid, Madrid, Spain
Received:
5
May
2023
Accepted:
8
October
2023
Published online:
19
October
2023
In practical quantum error correction implementations, the measurement of syndrome information is an unreliable step—typically modeled as a binary measurement outcome flipped with some probability. However, the measured syndrome is in fact a discretized value of the continuous voltage or current values obtained in the physical implementation of the syndrome extraction. In this paper, we use this “soft” or analog information to benefit iterative decoders for decoding quantum low-density parity-check (QLDPC) codes. Syndrome-based iterative belief propagation decoders are modified to utilize the soft syndrome to correct both data and syndrome errors simultaneously. We demonstrate the advantages of the proposed scheme not only in terms of comparison of thresholds and logical error rates for quasi-cyclic lifted-product QLDPC code families but also with faster convergence of iterative decoders. Additionally, we derive hardware (FPGA) architectures of these soft syndrome decoders and obtain similar performance in terms of error correction to the ideal models even with reduced precision in the soft information. The total latency of the hardware architectures is about 600 ns (for the QLDPC codes considered) in a 20 nm CMOS process FPGA device, and the area overhead is almost constant—less than 50% compared to min-sum decoders with noisy syndromes.
Key words: Quantum error correction / Syndrome-based decoding / FPGA devices
© The Author(s) 2023
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